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I NTEGRATED C IRCUITS D IVISION
The inductor peak current rating is given by:
I Lmax = I LED ? ? 1 + ? 0.5 ? r iout ? ?
2.2.7 Gate Output Drive
The MXHV9910 uses an internal gate drive circuit to
turn on and off an external power MOSFET. The gate
driver can drive a variety of MOSFETs. For a typical
off-line application, the total MOSFET gate charge will
be less than 25nC.
MXHV9910
2.2.8 Linear Dimming
A linear dimming function can be implemented by
applying a DC control voltage to the LD pin. By varying
this voltage, the user can adjust the current level in the
LEDs, which in turn will increase or decrease the light
intensity. The control voltage to the LD pin can be
generated from an external voltage divider network
from V DD . This function is useful if the user requires a
LED current at a particular level and there is no exact
R sense value available. N ote that applying a voltage
higher than the current sense threshold voltage at the
LD pin will not change the output current due to the
fixed threshold setting. When the LD pin is not used, it
should be connected to V DD .
Figure 5 Typical Linear Dimming Application Circuit
F u se F2
2A
BR1
LD
Monitor
AC Inp u t
90 - 265 V rms
NTC1
AC
AC
-
+
D1
BY V 26B
C1
0.1 μ F
400 V
C2
22 μ F
400 V
R1
402k Ω
MXH V 9910
R2
51k Ω
HB LEDs
350mA
L1
4.7mH
IXTA 8 N50P
V IN
CS
GND
GATE
R T
LD
V DD
P W MD
RA1
5.0k Ω
C3
C4
2.2.9 PWM Dimming
R3
0.56 Ω
2.2 μ F
16 V
0.1 μ F
25 V
Pulse width modulation dimming can be implemented
by driving the PWMD pin with a low frequency square
wave signal in the range of a few hundred Hertz. The
PWMD signal controls the LED brightness by gating
the PWM gate driver output pin GATE.
The signal can be generated by a microcontroller or a
pulse generator with a duty cycle proportional to the
amount of desired light output. When PWMD is low,
gate drive is off; when PWMD is high, gate drive is
enabled.
Figure 6 Buck Driver for PWM Dimming Application Circuit
V IN
D1 Schottky
40 V
HB LEDs
900mA Max
12 - 30 V DC
10 μ F
50 V
220 μ H
MXH V 9910
402k Ω
ASMT-Mx00
V IN
CS
R T
LD
Q1
GND
GATE
V DD
P W MD
CPC1001N*
8
R1
0.27 Ω
0.1 μ F
50 V
www.ixysic.com
*Optional Isolation
P W M
R03
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